1. Field of the Invention
This invention relates to a complementary-symmetry metal-oxide semiconductor device (hereinafter referred to as a "CMOS device").
2. Description of the Prior Art
In recent years, an increasing demand has been made for a CMOS device which has various merits such as low power consumption and stability with respect to power source voltage fluctuations. Formerly, the CMOS device has had some drawbacks. At present, however, the defects, except for the latch-up phenomenon, have been resolved. With a P well type CMOS device, the latch-up phenomenon designates an objectionable condition in which current can flow freely from a power source VDD to the ground VSS through a lateral type parasitic PNP transistor appearing in an N type substrate and a vertical parasitic NPN transistor appearing in a P well. Both parasitic transistors are connected together at the base and collector regions, creating a PNPN thyristor. When the thyristor is rendered conductive by external electrical noise, a current begins to flow and continues at an increasing rate, until the power source VDD is cut off. As a result, the original function of the CMOS device is impaired, possibly causing the CMOS device to be destroyed by the high heat arising from the flow of large currents.
As described above, the occurrence of the latch-up phenomenon results when a thyristor is rendered conductive by external noises incident on the device over a long period of time. Therefore, the prevention of the latch-up phenomenon consists in the suppression of the occurrence of at least one of the above-mentioned factors. A conventional process for avoiding the latch-up phenomenon comprises separating the MOS regions of the respective channel types in order to suppress the formation of a thyristor. A CMOS/SOS device constructed by mounting a CMOS element on a sapphire substrate is a typical example of the above-mentioned process. However, this device has the drawback that its manufacture involves a complicated process.
Another conventional process proposed for the suppression of the latch-up phenomenon comprises constructing a device by interposing an insulation layer between the respective MOS regions. However, this process is accompanied by the drawback that the degree of integration is reduced. Still another conventional process comprises extending the base region of a transistor to suppress the condition which may lead to the conduction of a thyristor. This process indeed has the advantages that because the degree of current amplification by a transistor drops with increasing conduction length, the thyristor is less likely to be rendered conductive. But the last mentioned process still has the drawback that the degree of integration is decreased.